1. Field of the Invention
The present invention relates to parallel/serial conversion circuits, serial/parallel conversion circuits and systems including such circuits.
2. Description of the Background Art
Parallel/serial conversion circuits and serial/parallel conversion circuits are widely used for ICs (Integrated Circuits) for communication, ICs incorporating memories such as RAM (Random Access Memory), ROM (Read Only Memory) or the like, and other various circuits.
FIG. 8 is a diagram showing an example of construction of a conventional parallel/serial conversion circuit. The parallel/serial conversion circuit 10a shown in FIG. 8 includes n register circuits 11 connected in serial. n represents a positive integer herein. The register circuits 11 each include a master latch 12 and a slave latch 13.
There are provided n parallel input terminals correspondingly to the n register circuits 11. The master latch 12 in each register circuit 11 is connected to a corresponding parallel input terminal 16. The slave latch 13 in the register circuit 11 of the final stage is connected to a serial output terminal 14.
Each master latch 12 includes a switch S11, a parallel input switch S13, an inverter G11 and a weak inverter G12. The switch S11 is connected between a node n11 connected to the slave latch 13 of the preceding stage and a node n12. The switch S13 is connected between a corresponding parallel input terminal 16 and the node n12. The inverter G11 is connected between the node 12 and a node n13, while the weak inverter G12 is connected to the inverter G11 in antiparallel between the node n13 and the node n12.
The ratio of the gate width to the gate length of a transistor constituting the weak inverter G12 is set to be about 1/5 the ratio of the gate width to the gate length of a transistor constituting the inverter G11. Thus, the weak inverter G12 will have a current driving capability about 1/5 that of the inverter G11. The inverter G11 and the weak inverter G12 form a ratio latch L11.
Each slave latch 13 includes a switch S12, an inverter G13, and a weak inverter G14. The switch S12 is connected between the node n13 and a node n14. The inverter G13 is connected between the node n14 and a node n15, while the weak inverter G14 is connected to the inverter G13 in antiparallel between the node n15 and the node n14.
The weak inverter G14, as is the case with the weak inverter G12, has a current driving capability about 1/5 that of the inverter G13. The inverter G13 and the weak inverter G14 form a ratio latch L12.
The switch S11 in each master latch 12 is controlled by a control signal S1 output from an AND gate G10. One input terminal of the AND gate G10 is provided with a first clock signal CLK1, while the other input terminal is provided with a trigger clock signal /TRG. The switch S13 in each master latch 12 is controlled by a trigger clock signal TRG. Further, the switch S12 in each slave latch 13 is controlled by a second clock signal CLK2.
The first and second clock signals CLK1, CLK2 may be clock signals of two phases, or clock signals of a single phase. The trigger clock signal /TRG is an inverted signal of the trigger clock signal TRG.
Parallel input signals DI (0)-DI (n-1) are provided correspondingly to the parallel input terminals 16. A serial signal is output from the serial output terminal 14.
Now, a description of an operation of the parallel/serial conversion circuit shown in FIG. 8 follows in conjunction with a timing chart in FIG. 9.
In a cycle CY1, when the first clock signal CLK1 and the trigger clock signal TRG are pulled to "H", the switch S13 in each master latch 12 is turned on. Thus, the parallel input signal DI (m) is taken up and latched by the ratio latch L11.
When the second clock signal CLK2 rises to "H", the switch S12 in each slave latch 13 is turned on. Thus, the signal latched in the ratio latch L11 in each mater latch 12 is provided to the ratio latch L12 and latched.
In a cycle CY2, the first clock signal CLK1 rises to "H", and the trigger clock signal TRG remains to be "L". This causes the control signal S1 to rise to "H". Therefore, the switch S11 in each master latch 12 is turned on. Thus, the signal latched in the slave latch 13 of the preceding stage is applied to the ratio latch L11 and latched therein.
Then, when the clock signal CLK2 rises to "H", the switch 12 in each slave latch 13 is turned on. This causes the signal latched in the ratio latch L11 in each master latch 12 applied to the ratio latch L12 in each slave latch 13 and latched therein.
In cycles CY3-CYn, the same operation as the cycle CY2 is conducted.
As described above, the parallel input signals DI (0)-DI (n-1) input in response to the trigger clock signal TRG are shifted within a plurality of register circuits 11 in response to the first and second clock signals CLK1, CLK2, and sequentially output as the serial signal from the serial output terminal 14.
FIG. 11 is a diagram showing one example of a construction of a conventional serial/parallel conversion circuit The serial/parallel conversion circuit 20a shown in FIG. 11 includes n register circuits 21 connected in serial. Each register circuit 21 includes a master latch 22, a slave latch 23, and a parallel output latch 24. The master latch 22 and the slave latch 23 are connected in serial, and the parallel output latch 24 is connected to the connection point of the master latch 22 and the slave latch 23.
The serial/parallel conversion circuit 20a has n parallel output terminals 27 for outputting n parallel output signals DO (0)-DO (n-1). The parallel output latch 24 in each register circuit 21 is connected to a corresponding parallel output terminal 27. The master latch 22 in the register circuit 21 in the first stage is connected to the serial input terminal 25.
Each master latch 22 includes a switch S21, an inverter G21, and a weak inverter G22. The switch 21 is connected between a node n21 connected to the slave latch 23 of the preceding stage and a node n22. The inverter G21 is connected between the node n22 and a node n23, while the weak inverter G22 is connected in antiparallel to the inverter G21 between the node n23 and the node n22.
The weak inverter G22 has a current driving capability about 1/5 that of the inverter G21. The inverter G21 and the weak inverter G22 constitute a ratio latch L21.
Each slave latch 23 includes a switch S22, an inverter G23, and a weak inverter G24. The switch S22 is connected between the node n23 and a node n24. The inverter G23 is connected between the node n24 and a node n25, while the weak inverter G24 is connected to the inverter G23 in antiparallel between the node n25 and the node n24.
The weak inverter G24, as is the case with the weak inverter G22, has a current driving capability about 1/5 that of the inverter G23. The inverter G23 and the weak inverter G24 constitute a ratio latch L22.
Each parallel output latch 24 includes a parallel output switch S23, an inverter G25, and a weak inverter G26. The switch S23 is connected between the node n23 and a node n26. The inverter G25 is connected between the node n26 and a node n27, while the weak inverter G26 is connected in antiparallel to the inverter G25 between the node n27 and the node n26.
The weak inverter G26, as is the case with the weak inverter G22, has a current driving capability about 1/5 that of the inverter G25. The inverter G25 and the weak inverter G26 constitute a ratio latch L23.
The switch S21 in each master latch 22 is controlled by a first clock signal CLK1. The switch S22 in each slave latch 23 is controlled by a control signal S2 output from an AND gate G20. One input terminal of the AND gate G20 is provided with a second clock signal CLK2, and the other input terminal is provided with a trigger clock signal /TRG. The switch S23 in each parallel output latch 24 is controlled by a trigger clock signal TRG.
Now a description of an operation of the serial/parallel conversion circuit 20a in FIG. 11 follows in conjunction with a timing chart in FIG. 12.
In a cycle CY1, when the first clock signal CLK1 rises to "H", the switch S21 in each master latch 22 is turned on. Thus, the signal latched in the slave latch 23 of the preceding stage is provided to the ratio latch L21 in the master latch 22 and latched.
Then, when the second clock signal CLK2 rises to "H", the control signal S2 also rises to "H". Thus, the switch S22 in each slave latch 23 is turned on. Consequently, the signal latched in the ratio latch L21 in each master latch 22 is provided to the ratio latch L22 in each slave latch 23 and latched.
In cycles CY2-CYn-1, the same operation as the cycle CY1 is conducted.
In a cycle CYn, when the first clock signal CLK1 rises to "H", the switch S21 in each master latch 22 is turned on. Thus, the signal latched in the slave latch 23 of the preceding stage is provided to the ratio latch L21 in each master latch 22 and latched.
Then, when the second clock signal CLK2 and the trigger clock signal TRG rise to "H", the control signal S2 output from the AND gate G20 remains to be "L" without any change. Therefore, the switch S22 in each slave latch 23 is not turned on, while the switch S23 in each parallel output latch 24 is turned on. Thus, the signal latched in the ratio latch L21 in each master latch 22 is provided to the ratio latch L23 in each parallel output latch 24 and latched.
As described above, the serial signal provided to the serial input terminal 25 is shifted within a plurality of register circuits 21 in response to the first and second clock signals CLK1, CLK2, and output as the parallel output signals DO (0) to DO (n-1), in response to the trigger clock signal TRG.
In the parallel/serial conversion circuit 10a in FIG. 8, the control signal S1 for controlling the switch S11 in each master latch 12 is provided by an AND operation of the first clock signal CLK1 and the trigger clock signal /TRG. Therefore, as indicated by a broken line in FIG. 10, timings for a first clock signal CLK1 and a trigger clock signal /TRG are shifted from each other, resulting in a problem.
More specifically, if the trigger clock signal /TRG falls before the first clock signal CLK1 rises, and the trigger clock signal /TRG rises before the first clock signal CLK1 falls, a pulse as depicted by the broken line is generated in the control signal S1.
As a result, after the switch S13 in each master latch 12 is turned on during a period T1 in which the trigger signal TRG is in an "H" level, the switch S11 is turned on in a period T2 in which the control signal S1 is in an "H" level. Thus, the parallel input signal input to the ratio latch L11 by the conduction of the switch S13 can be replaced with a signal provided from the slave latch 13 of the preceding stage by the conduction of the switch S11.
Thus, erroneous operations can possibly take place in the parallel/serial conversion circuit 10a shown in FIG. 8.
In the serial/parallel conversion circuit 20a in FIG. 11, the control signal S2 for controlling the switch S22 in each slave latch 23 is provided by an AND operation of the second clock signal CLK2 and the trigger clock signal /TRG. Therefore, as indicated by the broken line shown in FIG. 13, a problem is encountered when timings for the second clock signal CLK2 and the trigger clock signal /TRG are shifted from each other.
More specifically, when the trigger clock signal /TRG falls after the second clock signal CLK2 rises, and the trigger clock signal /TRG rises after the second clock signal CLK2 falls, a pulse as depicted by the broken line in the figure is generated in the control signal S2.
As a result, after the switch S22 in each slave latch 23 is turned on during a period T3 in which the control signal S2 is in an "H" level, the switch S23 in each parallel output latch 24 is turned on during a period T4 in which the trigger clock signal TRG is in "H" level. Consequently, after the inverter G21 in the ratio latch L21 drives the inverter G23 by the conduction of the switch S22 while competing with the weak inverter G24 in the ratio latch L22, the inverter G21 in the ratio latch L21 will drive the inverter G25 by the conduction of the switch 23 while competing with the weak inverter G26. Therefore, the signal held in the ratio latch L23 will become unstable.
As described above, in the serial/parallel conversion circuit 20a in FIG. 11, erroneous operations can possibly take place by the shifting of the trigger signal /TRG.